The present invention relates generally to integrated circuits, and more particularly, to pin level access to general purpose input/output (GPIO) pins by one or more cores or an integrated circuit.
Multi-core systems include various types of cores, like graphic processors, general purpose processors, and digital signal processors (DSP), integrated on a single integrated circuit (IC). The cores communicate with external devices by way of input/output (I/O) pins. Recent developments have led to a requirement of low power-consumption, which in one way is achieved by a decrease in the size of ICs. This has in turn led to a restriction on the number of I/O pins. Hence, it is necessary to use the available I/O pins efficiently. It also is necessary to ensure low-latency and high accuracy in the communication between the cores and the connected external devices. Further, multiple cores may generate multiple access requests for an I/O pin. Hence, it is necessary to prevent conflicts amongst the cores and the pins. Thus, access to the I/O pins by the cores is controlled with a control system.
In one known technique, an IC having multiple cores has a control system that includes an I/O bank with a set of I/O pins and software-implemented control logic to control access to the I/O pins, and thus, has software-level synchronization of access to the I/O pins. The software manages and assigns a state to each of the I/O pins, and the state of each of the I/O pins is known to all of the cores. Each of the I/O pins is in a locked state when a core accesses it, and in a free state when it is not being accessed by any of the cores. If a first core wants to write data to an external device, first it checks the state of a first I/O pin. When the first I/O pin is free, the first core provides the write data to the external device by way of an I/O register of an I/O bank. The first core then changes the state of the first I/O pin to the locked state. The I/O register stores the write data as pin data. Thus, the first core updates the pin data with the write data. If a second core wants to communicate with a second external device, then the second core generates an access request to access the I/O register. However, the second core cannot will not be able to access the first I/O pin because it is in the locked state, so the second core has to wait until the state of the first I/O pin changes from the locked state to the free state. This introduces software latency, which impacts system performance.
One way to overcome the software latency problem is to allocate a dedicated I/O bank to each core or core type. Thus, first and second cores of first and second types are allocated first and second I/O banks, respectively, which have corresponding first and second I/O registers. The control system then includes a control logic circuit. A first external device is connected to a first I/O pin of the first I/O bank, and a second external device is connected to a first I/O pin of the second I/O bank. The first and second cores are not supposed to access the second and first I/O banks, respectively (that is, they only access their own I/O bank). This allows the second core to control the second external device without a delay caused by the first core accessing a first external device. However, a problem arises when the number of external devices controlled by the first core is greater than the number of I/O pins available in the first I/O bank. Further, the number of external devices controlled by the second core may be less than the number of I/O pins available in the second I/O bank, so some of the I/O pins of the second I/O bank are unused. Further, to enable access to the first external device by the second core, the first external device must be disconnected from the first I/O pin of the first I/O bank and then connected to a second I/O pin of the second I/O bank. As the first and second cores, the additional control logic IC, and the first and second external devices are mounted on a single PCB, the disconnection and reconnection of the first external device requires modifications to the PCB wiring, which is undesirable. Further, if the first and second I/O registers are located in a memory shared by the first and second cores, it is possible that the first I/O register could be updated by the second core, resulting in corruption of the first I/O register pin data.
U.S. Pat. No. 6,532,533 ('533) discloses a technique to overcome the aforementioned problem. The technique includes storing pin data (i.e., contents of an I/O register) corresponding to an I/O bank in each of first and second memories allocated to first and second cores, respectively. The '533 patent further discloses assigning first and second sets of the I/O pins to the first and second cores, respectively. The first set of I/O pins includes first and second I/O pins of an I/O bank, and the second set of I/O pins includes third and fourth I/O pins of the I/O bank. The first and second cores generate first and second write data that is output on the first and second sets of I/O pins, respectively. The '533 patent further discloses that the control logic circuit generates first and second mask data corresponding to the first and second cores to selectively mask bits of the pin data. The control logic circuit updates bits of the pin data that correspond to the first set of I/O pins with bits of the first write data, and masks bits of the pin data that do not correspond to the first set of I/O pins. Each of the first and second cores stores the first and second mask data in the corresponding memory allocated thereto. Thus, the mask data corresponding to all the cores and the pin data is duplicated. Hence, this technique involves the use of a significant amount of memory space, which is undesirable. Further, if the software running on the first core introduces an error in the first mask, the first core may modify the first mask data to include the third I/O pin in the first set of I/O pins. Since the third I/O pin is pre-allocated to the second core, the second write data provided to the third I/O pin could get corrupted. Since the second core may execute software that is different and independent of the software running on the first core, this data corruption is difficult to debug.
It would be advantageous to have an IC that provides write access of a core to an I/O pin without delay and pin data corruption.